1. Field of the Invention
The present invention generally relates to the manufacture of very large scale integrated (VLSI) circuit devices and, more particularly, to the coding of relative dose information onto design data to allow continuous line width variation for all features without impact to data volume.
2. Background Description
Manufacturing of semiconductor devices is dependent upon the accurate replication of computer aided design (CAD) generated patterns onto the surface of a device substrate. The replication process is typically performed using optical lithography followed by a variety of subtractive (etch) and additive (deposition) processes. Optical lithography patterning involves the illumination of a metallic coated quartz plate known as a photomask which contains a magnified image of the computer generated pattern etched into the metallic layer. This illuminated image is reduced in size and patterned into a photosensitive film on the device substrate.
As a result of the interference and processing effects which occur during pattern transfer, images formed on the device substrate deviate from their ideal dimensions and shape as represented by the computer images. These deviations depend on the characteristics of the patterns as well as a variety of process conditions. Because these deviations can significantly effect the performance of the semiconductor device, many approaches have been pursued which focus on CAD compensation schemes which ensure a resultant ideal image.
The performance enhancement of advanced VLSI circuitry (that is, the speed enhancement versus dimension reduction of the circuits) is increasingly limited by the lack of pattern fidelity in a series of lithography and RIE processes at small dimensions (e.g., sub 0.5 .mu.m). In the photolithography process, a pattern is transferred from a photo mask to a photosensitive film (resist) on the wafer. In the RIE process, this pattern in the resist is transferred into a variety of films on the wafer substrate.
An alternative to the costly development of processes with ever higher effective resolution is the selective biasing of mask patterns to compensate for the pattern distortions occurring during wafer processing. The term Optical Proximity Correction (OPC) is commonly used to describe this process of selective mask biasing, even though the trend exists to include pattern distortions unrelated to the optical image transfer. The idea of biasing patterns to compensate for image transfer infidelities has been commonly applied to E-beam lithography to counteract the effects of back scattered electrons, both in the writing of photo masks and in direct wafer writing operations. See for example U.S. Pat. No. 5,278,421.
OPC extends the use of the automatic pattern biasing concept to the two major pattern transfer processes used in VLSI technologies. Current implementations of OPC can be categorized as "rules-based" in which patterns are sorted and biased in the computer aided design (CAD) data set based on rules relating bias amounts to pattern attributes such as size, proximity, and density, and "convolution-based" in which CAD patterns are biased based on particular pattern environment. Both the rules and convolution functions can be generated either from process simulations or from empirical data. For examples of "rules-based" OPC implementations, see Richard C. Henderson and Oberdan W. Otto, "CD data requirements for proximity effect corrections", 14th Annual BACUS Symposium on Photomask Technology and Management, William L. Brodsky and Gilbert V. Shelden, Editors, Proc. SPIE 2322 (1994), pp.218-228, and Oberdan W. Otto, Joseph G. Garofalo, K. K. Low, Chi-Min Yuan, Richard C. Henderson, Christophe Pierrat, Robert L. Kostelak, Shiela Vaidya, and P. K. Vasudev, "Automated optical proximity correction--a rules-based approach", Optical/Laser Microlithography VII, Timothy A. Brunner, Editor, Proc. SPIE 2197 (1994), pp. 278-293. For examples of the "convolution-based" OPC implementations, see John P. Stirniman and Michael L. Rieger, "Fast proximity correlation with zone sampling", Optical/Laser Microlithography VII, Timothy A. Brunner, Editor, Proc. SPIE 2197 (1994), pp. 294-301, and John Stirniman and Michael Rieger, "Optimizing proximity correction for wafer fabrication processes", 14th Annual BACUS Symposium on Photomask Technology and Management, William L. Brodsky and Gilbert V. Shelden, Editors, Proc. SPIE 2322 (1994), pp. 239-246.
These compensation schemes have concentrated on manipulation of the computer representations by adding, subtracting, or biasing design features. Modification of the designs with computer programs have become routine; however, the manufacturing of the photomask to acceptable criteria has proven to be difficult due to image fidelity and data processing constraints. These constraints arise due to the relationship of the allowable compensation increments in the design of the photomask data volumes and processing times. Reduced design compensation increments increase data volumes and processing times, making some designs extremely difficult and costly to replicate. On the other hand, compensation increments which are too large will not allow for acceptable corrections to the final image, producing a nonfunctional or poorly performing device.
In a typical compensation scheme, CAD data in a hierarchical format using a discrete design grid is created which represents the ideal device patterns. Compensation information based on known patterning distortions is defined in a "lookup" table or convolution function. Manipulation of the CAD data based on the distortion knowledge is performed within an optical proximity correction (OPC) engine which outputs biased CAD data. The output data contains reduced hierarchy and design grid in order to allow for the appropriate compensations. The biased CAD data is then converted to a flat format for photomask fabrication.
Constraints which exist with design system manipulation and pattern replication are driving the consideration of other methods of correction such as mask process compensation. The process of fabricating a mask involves patterning a computer designed image onto the metallic layer of a photomask. This is accomplished by coating the metallic surface of the photomask with a polymer film which is sensitive to incident electron energy or optical exposure, depending on the type of exposure system. The coated photomask blank is placed in the exposure system which draws the pattern based on a digitized formal of the CAD layout which instructs the exposure system to turn on or turn off energy. The resultant photomask contains a polymer film with irradiated areas that correspond to the CAD data. Due to the chemical make-up of the polymer, a reaction occurs in these areas that change the polymer solubility relative to the non-irradiated regions. By placing the photomask into an appropriate solution, the irradiated polymer can be removed while retaining the non-irradiated region. This process is known as developing. It is possible to remove the non-irradiated area if a polymer is selected with the appropriate chemistry. Following this process, a second chemical step can be used to remove the uncovered metallic region, known as etching, leaving only an image of the CAD representation of the device layer on the photomask.
Within this process, many parameters effect the size of images created, such as incident energy level, duration of development, or duration of the etch step. Processes such as development or etch effect all regions of the photomask and are used to adjust the average size of all the features contained in the design. Energy level or does is controlled by the exposure system which can selectively apply an energy level to any particular pattern needing compensation. It has been shown that a linear region exists for image size control as a function of dose making selective process biasing possible.
Current approaches, based on the modification of the CAD data set, are intrinsically confined to the granularity of the minimum addressable design grid allowed by the mask maker. A design grid of 1/40 .mu.m is an aggressive design, limiting the minimum displacement of any feature edge to 25 nm. A requirement by chip designers to fix the center line of all features dictates that two edges of a line have to be shifted simultaneously in opposite directions, further limiting the minimum change in feature size to 50 nm. As a reference, 50 nm constitutes the entire line width tolerance budget for the 250 nm technologies (e.g., 256MB DRAMs), making line width control to 50 nm biasing impossible. Reducing the grid size to smaller than 1/40 .mu.m grid has tremendous impact on data volume and mask write times, making it impossible to write full product chips on current mask writers at anything smaller than 1/80 .mu.m grid size. Biasing line widths at 25 nm granularity will still not achieve the required level of line width control.
In addition to data volume increases caused by a decrease in allowable address size (design grid), data unnesting (loss of hierarchical data structure), unavoidable to a certain degree in design data manipulation based on OPC, also increases data volume both for design systems and postprocessing tools.